58 research outputs found

    Improved Reliability of FPGA-based PUF Identification Generator Design

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    FPGA-based Strong PUF with Increased Uniqueness and Entropy Properties

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    Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays

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    As the network-on-chip (NoC) integrated into an SoC design can come from an untrusted third party, there is a growing risk that data integrity and security get compromised when supposedly sensitive data flows through such an untrusted NoC. We thus introduce a new method that can ensure secure and secret data transmission over such an untrusted NoC. Essentially, the proposed scheme relies on encoding binary data as delays between packets travelling across the source and destination pair. The maximum data transmission rate of this inter-packet-delay (IPD)-based communication channel can be determined from the analytical model developed in this article. To further improve the undetectability and robustness of the proposed data transmission scheme, a new block coding method and communication protocol are also proposed. Experimental results show that the proposed IPD-based method can achieve a packet error rate (PER) of as low as 0.3% and an effective throughput of 2.3×105\boldsymbol {2.3\times 10^{5}} b/s, outperforming the methods of thermal covert channel, cache covert channel, and circuit-based encryption and, thus, is suitable for secure data transmission in unsecure systems

    Ultra-Compact and Robust FPGA-Based PUF Identification Generator

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    A unique and robust single slice FPGA identification generator

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    A Machine Learning Attack Resistant Multi-PUF Design on FPGA

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    Novel lightweight FF-APUF design for FPGA

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